Nonlinear resistor circuit using capacitively-coupled multi-input MOSFETS

ABSTRACT

A nonlinear resistor circuit utilizes capacitively-coupled multi-input MOSFETs in order to enable integration thereof by a standard CMOS process, and which can realize two types of nonlinear resistance characteristics; i.e., A-type and V-type nonlinear resistance characteristics. The circuit includes a core circuit which comprises enhancement-type N-channel and P-channel MOSFETs with source terminals being connected with each other.

TECHNICAL FIELD

The present invention relates to a nonlinear resistor circuit usingcapacitively-coupled multi-input MOSFETS, and more particularly to anonlinear negative resistor circuit using capacitively-coupledmulti-input MOSFETs.

BACKGROUND ART

Devices and circuits having a nonlinear current-voltage (I-V)characteristic, especially those having a negative resistancecharacteristic, play important roles in logic circuits, memory circuits,oscillators, impedance conversion circuits, various nonlinear signalprocessing circuits, and chaos generators.

There have been proposed various types of such devices, including adevice circuit having a Λ-type I-V characteristic and realized throughcombined use of bipolar junction transistors (BJTs) and/or field effecttransistors (FETs) (First reference: L. O. Hill, D. O. Pederson, and R.S. Pepper, “Synthesis of Electronic Bistable Circuits,” IEEETransactions on Circuit Theory, vol. CT-10, pp. 25-35, 1963).

Further, a method of effectively realizing the circuit throughemployment of a technique for integrating two junction FETs (J-FETs) hasbeen proposed (Second reference: G. Kano and H. Iwasa, “A new A-typeNegative Resistance Device of Integrated Complementary FET Structure,”IEEE Transactions. Electron Devices, vol. 21, no. 7, pp. 448-449, 1974).

Moreover, a Λ-type transistor circuit that realizes a Λ-type negativeresistance characteristic by use of two MOSFETs has been proposed andapplied to an impedance conversion circuit and a neuron circuit (Thirdreference: Kennosuke Sugisaki, Hisahiro Sekine, Yoshifumi Sekine, KoheiNakamura, and Masatoshi Suyama, “A Λ-type transistor using twoMOS-FETs,” Proc. Denki-Kankei-Gakkai, Tohoku-shibu Rengo-Taikai, 2G9, p.270, 1978; Fourth reference: Hisahiro Sekine, Kennosuke Sugisaki,Hitoshi Sato, Yoshifumi Sekine, and Masatoshi Suyama, “The equivalentinductance using a Λ-type transistor,” IEICE Trans., vol. J63-C, no. 5,pp. 325-327, 1980; and Fifth reference: Hoshifumi Sekine, MasahikoNakamura, Toshiyuki Ochiai, and Masatoshi Suyama, “Utilization of aΛ-type transistor for a hardware neuron model,” IEICE Trans., vol.J68-A, no. 7, pp. 672-679, 1985).

DISCLOSURE OF THE INVENTION

The above-described conventional circuit cannot be integrated by astandard CMOS process in which only enhancement-type MOSFETs areavailable, because at least one of the MOSFETs in the circuit must be ofa depletion type,

An object of the present invention is to provide a nonlinear resistorcircuit which utilizes capacitively-coupled multi-input MOSFETs in orderto enable integration thereof by a standard CMOS process, and which canrealize two types of nonlinear resistance characteristics; i.e., Λ-typeand V-type nonlinear resistance characteristics. Thus, the presentinvention solves the above-described problems.

The capacitively-coupled multi-input MOSFET comprises a MOSFET and aplurality of capacitors which are connected to the gate terminal inparallel and provide a number of input terminals. The operation of thecapacitively-coupled multi-input MOSFET can be controlled throughcontrol of voltage applied to one or more of the capacitively-coupledinput terminals. The structure of the circuit is the same as amulti-input floating gate MOSFET, which effects a linear weightedsummation of input, such as a VMOSFET (see Sixth reference; T. Shibataand T. Ohmi, “A Functional MOS Transistor Featuring Gate-level WeightedSum and Threshold Operations,” IEEE Transactions. Electron Devices, vol.39, no. 6, pp. 1444-1455, 1992) and an MFMOSFET (see Seventh reference:H. R. Mehrvarz and C. Y. Kwok, “A Novel Multi-Input Floating-Gate MOSFour-Quadrant Analog Multiplier,” IEEE J. of Solid State Circuits, vol.31, no. 8, pp. 1123-1131, 1996).

Since such linear summation does not play an important role in thenonlinear resistor circuit of the present invention, the input couplingcapacitors are not required to have linear characteristics. Therefore,as used herein, the term “capacitively-coupled multi-input MOSFET”refers to a more general circuit configuration, including a VMOSFET.Therefore, the nonlinear resistor circuit according to the presentinvention can be integrated by a less-expensive CMOS process in whichlinear capacitors are not available.

Further, the size of the nonlinear resistor circuit according to thepresent invention can be reduced if a floating gate device such as aVMOSFET can be used.

In order to achieve the above object, the present invention provides:

[1] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs, comprising a core circuit which has a nonlinear resistancecharacteristic and which comprises an enhancement-type first-channelMOSFET having a capacitively-coupled multi-input gate terminal, and anenhancement-type second-channel MOSFET having a capacitively-coupledmulti-input gate terminal, the source terminals of the MOSFETs beingconnected with each other.

[2] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs as described in [1] above, wherein the first channel of the corecircuit is an N channel, and the second channel of the core circuit is aP channel, so that a Λ-type current-voltage characteristic is obtained.

[3] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs as described in [2] above, wherein the Λ-type current-voltagecharacteristic is varied through application of an external controlvoltage.

[4] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs as described in [3] above, wherein, as shown in FIGS. 6(a)-6(p),a fifth potential (v_(X)) is provided between the drain terminal (A) ofthe N-channel MOSFET and a first input/output terminal (X); a sixthpotential (V_(Y)) is provided between the drain terminal (B) of theP-channel MOSFET and a second input/output terminal (Y); a firstpotential (v_(P1A), v_(P1X)) is provided between the drain terminal (A)of the N-channel MOSFET and a first capacitor (C_(P1)) connected to thegate of the P-channel MOSFET or between the first input/output terminal(X) and the first capacitor (C_(P1)); a second potential (V_(P2B),V_(P2Y)) is provided between the drain terminal (B) of the P-channelMOSFET and a second capacitor (C_(P2)) connected to the gate of theP-channel MOSFET or between the second input/output terminal (Y) and thesecond capacitor (C_(P2)); a third potential (v_(N1B), v_(N1Y)) isprovided between the drain terminal (B) of the P-channel MOSFET and athird capacitor (C_(N1)) connected to the gate of the N-channel MOSFETor between the second input/output terminal (Y) and the third capacitor(C_(N1)); and a fourth potential (v_(N2B), v_(N2Y)) is provided betweenthe drain terminal (B) of the P-channel MOSFET and a fourth capacitor(C_(N2)) connected to the gate of the N-channel MOSFET or between thesecond input/output terminal (Y) and the fourth capacitor (C_(N2)).

[5] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs as described in [1] above, wherein the first channel of the corecircuit is a P channel, and the second channel of the core circuit is anN channel, so that a V-type current-voltage characteristic is obtained.

[6] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs as described in [5] above, wherein the V-type current-voltagecharacteristic is varied through application of an external controlvoltage,

[7] A nonlinear resistor circuit using capacitively-coupled multi-inputMOSFETs as described in [6] above, wherein, as shown in FIGS. 8(a)-8(p),an eleventh potential (v_(X)) is provided between the drain terminal (B)of the P-channel MOSFET and a first input/output terminal (X); a twelfthpotential (v_(Y)) is provided between the drain terminal (A) of theN-channel MOSFET and a second input/output terminal (Y); a seventhpotential (v_(N2A), v_(N2X)) is provided between the drain terminal (B)of the P-channel MOSFET and a fifth capacitor (C_(N2)) connected to thegate of the N-channel MOSFET or between the first input/output terminal(X) and the fifth capacitor (CN₂); an eighth potential (v_(N1A),v_(N1Y)) is provided between the drain terminal (A) of the N-channelMOSFET and a sixth capacitor (C_(N1)) connected to the gate of theN-channel MOSFET or between the second input/output terminal (Y) and thesixth capacitor (C_(N1)); a ninth potential (v_(P2A), v_(P2Y)) isprovided between the drain terminal (A) of the N-channel MOSFET and aseventh capacitor (C_(P2)) connected to the gate of the P-channel MOSFETor between the second input/output terminal (Y) and the seventhcapacitor (C_(P2)); and a tenth potential (v_(P1A), v_(P1Y)) is providedbetween the drain terminal (A) of the N-channel MOSFET and an eighthcapacitor (C_(P1)) connected to the gate of the P-channel MOSFET orbetween the second input/output terminal (Y) and the eight capacitor(C_(P1)).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an N-channel MOSFET having multiplecapacitively-coupled inputs according to the present invention.

FIG. 2 is a circuit diagram of a P-channel MOSFET; having mcapacitively-coupled inputs according to the present invention.

FIG. 3 is a diagram in relation to an embodiment of the presentinvention, showing a circuit which serves as a core of a nonlinearresistor circuit.

FIG. 4 is a diagram in relation to the embodiment of the presentinvention, showing a basic circuit which realizes a Λ-type I-Vcharacteristic.

FIG. 5 is a diagram in relation to the embodiment of the presentinvention, showing a basic circuit which realizes a V-type I-Vcharacteristic.

FIGS. 6(a)-6(p) are diagrams in relation to the embodiment of thepresent invention, each showing a nonlinear resistor circuit whichrealizes a A-type I-V characteristic.

FIG. 7 is a diagram in relation to another embodiment of the presentinvention, showing an exemplary nonlinear resistor circuit whichrealizes a Λ-type I-V characteristic.

FIGS. 8(a)-8(p) are diagrams in relation to the embodiment of thepresent invention, each showing a nonlinear resistor circuit whichrealizes a V-type I-V characteristic.

FIG. 9 is a diagram in relation to the embodiment of the presentinvention, showing an exemplary nonlinear resistor circuit whichrealizes a V-type I-V characteristic.

FIG. 10 is a graph showing results of a simulation in which variation ini_(Λ) with v_(XY) in the circuit of FIG. 7 was simulated, where v_(N1Y)and v_(X) are parameters.

FIG. 11 is a graph showing i_(Λ)-v_(XY) characteristics of the circuitof FIG. 7, where v_(Y) is a parameter.

FIG. 12 is a graph showing results of a simulation in which variation ini_(V) with v_(XY) in the circuit of FIG. 9 was simulated, where v_(N1Y)and v_(X) are parameters.

FIG. 13 is a graph showing i_(V)-v_(XY) characteristics of the circuitof FIG. 9, where v_(Y) is a parameter.

FIG. 14 is a graph in relation to the embodiment of the presentinvention, showing a variety of nonlinear resistance characteristics.

FIG. 15 is a graph showing results of a measurement in which variationin i_(Λ) with v_(XY) in the circuit of FIG. 7 was measured, wherev_(P2Y)=−4 V, v_(N2Y)=3.2 V, v_(P1A)=v_(Y)=0 V, and v_(N1Y) and v_(X)are parameters.

FIG. 16 is a graph showing results of a measurement in which variationin i_(Λ) with v_(XY) in the circuit of FIG. 7 was measured, wherev_(N1Y)=3.5 V, v_(P2A)=−4 V, v_(P1A)=v_(X)=0 V, v_(N2Y)=v_(Y), and v_(Y)is a parameter.

FIG. 17 is a graph showing v_(XY)-i_(Λ) characteristics of the circuitof FIG. 9, where v_(P2Y)=−4 V, and v_(N2B)=v_(P1Y)=v_(Y)=0 V, andv_(N1Y) and v_(X) are parameters.

FIG. 18 is a graph showing v_(XY)-i_(Λ) characteristics of the circuitof FIG. 9, where v_(P2Y)=−4 V, v_(N1Y)=3.2 V, v_(N2B)=v_(X)=0 V,v_(N2Y)=v_(Y), and v_(Y) is a parameter.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will next be described in detail.

[1] Capacitively-Coupled Multi-Input MOSFETs

FIG. 1 is a circuit diagram of a capacitively-coupled multi-inputN-channel MOSFET according to the present invention. As shown in FIG. 1,the capacitively-coupled multi-input N-channel MOSFET (referred to asNMOSFET hereinafter) includes an ordinary NMOSFET, and a plurality ofcapacitors C_(l) to C_(m) which are connected to a gate terminal G ofthe NMOSFET and serve as input terminals. Input voltages are applied viathe capacitors C_(l) to C_(m), and thus the gate terminal G of theNMOSFET MN becomes a floating gate.

Let the voltages of the source terminal S, the drain terminal D, thegate terminal G, and the body terminal B, with respect to ground, bev_(Sn), v_(Pn), v_(Gn), and v_(Bn), respectively. As shown in FIG. 1,v_(IN1), v_(IN2), v_(IN3), . . . , v_(1Nm) represents voltages appliedto the respective input terminals, with respect to ground. C₀ representsthe sum of the gate-oxide capacitance and all the parasitic capacitancessuch as gate-to-body capacitance, gate-to-drain capacitance, andgate-to-source capacitance. C₁, C₂, C₃, . . . C_(m) represent couplingcapacitances between the gate terminal and the respective inputterminals.

It is assumed that there is no leakage of electrical charge and that theinitial electrical charge of the gate terminal G is 0. In addition, itis assumed that the source terminal S and the body terminal B areconnected to each other. Furthermore, the parasitic capacitance C₀ isconsidered to have no qualitative influence on the characteristics ofthe circuits described below. Therefore, for simplicity of analysis, itis assumed that:

C ₀ <<C ₁ for i=1 to m  (1)

The approximate potential of the gate terminal G is given by:$\begin{matrix}{v_{G_{n}} \approx \frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}}} & (2)\end{matrix}$

where $\begin{matrix}{C_{T} = {\sum\limits_{i = 1}^{m}C_{i}}} & (3)\end{matrix}$

In the following, the threshold voltage of MN with respect to the sourceterminal S is denoted as v_(tn), the voltage between gate and source asv_(GSn)=v_(Gn)−v_(Sn), and voltage between drain and source asv_(DSn)=v_(Dn)−v_(Sn). In this case, a state of MN and a drain currenti_(Dn) are obtained as follows, depending on the relationship among thepotentials of the respective terminals.

1. When v_(DSn)<V_(tn), that is,${\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sn}} < {V_{tn}:}$

In this case, MN is in the cutoff region of operation. Therefore,

i _(Dn)=0.  (4)

2. When v_(GSn)v_(tn), that is,${\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sn}} \geq {V_{tn}:}$

In this case, MN is under inversion, so that i_(DN)≠0. Further, underthis condition, MN is in either the triode region or the saturationregion, depending on the voltage of the drain terminal.

In the following, the channel modulation effect is ignored forsimplicity and the voltage between the drain and the source is denotedas v_(DSn).

(a) When v_(DSn)<v_(GSn)−V_(tn), i.e.,$v_{DSn} < {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sn} - {V_{tn}:}}$

In this case, MN is in the triode region. Therefore, the drain currentis obtained from the following equation. $\begin{matrix}{i_{Dn} = {K_{n}\left\{ {{2\left( {v_{GSn} - V_{tn}} \right)v_{DSn}} - v_{DSn}^{2}} \right\}}} & (5) \\{\text{~~~~~} = {K_{n}\left\{ {{2\left( {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sn} - V_{tn}} \right)v_{DSn}} - v_{DSn}^{2}} \right\}}} & (6)\end{matrix}$

where K_(n)=(1/2)μ_(n)C_(ox)(W_(n)/L_(n)), μ_(n) is electron mobility,C_(ox) is the oxide capacitance of MN, and W_(n) and L_(n) are the gatewidth and channel length of MN (these are the same in the followingdescription).

(b) When v_(DSn)≧v_(GSn)−V_(tn), i.e.,$v_{DSn} \geq {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sn} - {V_{tn}:}}$

In this case, MN is in the saturation region. Therefore, the draincurrent is obtained from the following equations. $\begin{matrix}{i_{Dn} = {K_{n}\left( {v_{GSn} - V_{tn}} \right)}^{2}} & (7) \\{\text{~~~~~} = {K_{n}\left( {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sn} - V_{tn}} \right)}^{2}} & (8)\end{matrix}$

From the above analyses, a capacitively-coupled multi-input MOSFET isconsidered a device whose drain current can be determined from therelative relationships between input voltages v_(IN1).

[1-2] Capacitively-Coupled Multi-Input P-Channel MOSFET

FIG. 2 is a circuit diagram of a PMOSFET having m capacitively-coupledinput terminals according to the present invention. A source terminaland a body terminal are connected to each other, as in the case of aNMOSFET. In addition, Eq. (1) is given herein for simplicity.

In this case, voltage v_(GP) of the gate terminal G of MP with respectto ground is given by the following equation similar to Eq. (2).$\begin{matrix}{v_{G_{p}} \approx \frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}}} & (9)\end{matrix}$

Let the voltages of the source terminal S and the drain terminal D withrespect to ground be v_(SP) and v_(Dp), respectively. In addition, letthe threshold voltage of MP with respect to the source terminal S bev_(tn), the voltage between gate and source be v_(GSp)=v_(Gp)−v_(Sp),and voltage between drain and source be v_(DBp)=v_(Dp)−v_(Sp). Moreover,the channel modulation effect is ignored for simplicity. In this case,the drain current is i_(Dp) is given by the following analyses.

1. When v_(GSp)>_(tp), that is,${\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sp}} > {V_{tp}\text{:}}$

In this case, MP is in the cutoff region of operation. Therefore,

i _(Dp)=0.  (10)

2. When v_(GSp)≦V_(tp), that is,${\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sp}} \leq {V_{tp}\text{:}}$

In this case, MP is under inversion, so that i_(Dp)≠0. Further, underthis condition, MP is in either the triods region or the saturationregion, depending on the voltage of the drain terminal.

(a) When v_(DSp)>v_(GSp)−V_(tp), i.e.,$v_{DSp} > {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sp} - {V_{tp}\text{:}}}$

In this case, MP is in the triode region. Therefore, the drain currentis obtained from the following equation. $\begin{matrix}{i_{Dp} = {K_{p}\left\{ {{2\left( {v_{GSp} - V_{tp}} \right)v_{DSp}} - v_{DSp}^{2}} \right\}}} & (11) \\{\text{~~~~~} = {K_{p}\left\{ {{2\left( {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sp} - V_{tp}} \right)v_{DSp}} - v_{DSp}^{2}} \right\}}} & (12)\end{matrix}$

where K_(p)=(1/2)μ_(p)C_(ox)(W_(p)/L_(P)), μ_(p) is hole mobility,C_(ox) is the oxide capacitance of MP, and W_(p) and L_(P) are the gatewidth and channel length of MP (these are the same in the followingdescription).

(b) When v_(DSp)≦v_(GSp)−V_(tp), i.e.,$v_{DSp} \leq {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sp} - {V_{tp}\text{:}}}$

In this case, MP is in the saturation region, Therefore, the draincurrent is obtained from the following equations. $\begin{matrix}{i_{Dp} = {K_{p}\left( {v_{GSp} - V_{tp}} \right)}^{2}} & (13) \\{\text{~~~~~} = {K_{p}\left( {\frac{\sum\limits_{i = 1}^{m}\left( {C_{i} \cdot v_{INi}} \right)}{C_{T}} - v_{Sp} - V_{tp}} \right)}^{2}} & (14)\end{matrix}$

[2] Nonlinear Resistor Circuits Using Capacitively-Coupled Multi-InputMOSFET

Next will be described a circuit which comprises twocapacitively-coupled multi-input MOSFETs in order to achieve variousnonlinear resistance characteristics. The basic structure of the circuitwas determined with reference to the first reference through the thirdreference mentioned in the Background Art section.

[2-1] The Core Circuit

FIG. 3 is a circuit serving as a core of a nonlinear resistor circuitshowing an embodiment of the present invention.

The circuit comprises an NMOSFET (MN) having capacitively-coupled inputsand a PMOSFET (MP) having capacitively-coupled inputs, wherein thesource terminals of MN and MP are connected with each other. In FIG. 3,each FET has only 2 input terminals, but generally, it is assumed tohave n input terminals. In addition, body terminals are omitted in FIG.3 for simplicity. As shown in FIG. 3, the drain terminal of MN islabeled A and the drain terminal of MP is labeled B. Moreover, twocapacitors of MN are denoted as C_(N1) and C_(N2), two capacitors of MPas C_(P1) and C_(P2), and input terminals of these capacitors arelabeled N1, N2, P1, and P2 respectively. In the following sections, thecircuit will be referred to as a “core circuit.”

[2-2] Basic Circuit Configuration for Realizing Λ-shaped I-VCharacteristics

FIG. 4 is a basic circuit for realizing Λ-shaped I-V characteristicsshowing an embodiment of the present invention, where the section withina broken line is a core circuit.

Voltage sources are added to the input terminals of the core circuit asin FIG. 4 to thereby obtain Λ-shaped I-V characteristics between theterminals A and B. In this case, when the respective node points assumethe voltages shown in FIG. 4 with respect to the terminal B, the gateterminal voltages vane and v_(GnB)and v_(GpB) of MN and MP are obtained,by use of Eqs. (2) and (9), from the following equations.$\begin{matrix}{v_{GnB} = \frac{{C_{N1}v_{{N1}_{B}}} + {C_{N2}v_{N2B}}}{C_{N1} + C_{N2}}} & (15) \\{v_{GpB} = \frac{{C_{P1}\left( {v_{\Lambda \quad B} + v_{{P1}\quad \Lambda}} \right)} + {C_{P2}v_{P2B}}}{C_{P1} + C_{P2}}} & (16)\end{matrix}$

Furthermore, the gate-source voltage v_(GSn), the drain source voltagev_(DSn) of MN, and those of MP, i.e., v_(GSp) and v_(DSp) respectively,are given by following equations.

v _(GSn) =v _(GnB) −v _(MA)  (17)

v _(DAn)=v_(AB) −v _(MA)  (18)

v _(GSp) =v _(GpB) −v _(MB)  (19)

v _(DSp) =−v _(MB)  (20)

where v_(MB) is the voltage of a node M with respect to the terminal B.

The drain current of MN, i_(Dn), and that of MP, i_(Dp), are expressedas follows for three operating regions; i e., the cutoff, triode, andsaturation regions, by use of equations derived in section [1].

For MN;

1. MN is in the cutoff region when v_(GSn)<V_(tn). Therefore, from Eq.(17),

when v _(OnB) −v _(MB) <V _(tn),  (21)

i _(Dn)=0.  (22)

2. When v_(GSn)≧V_(tn), i.e.,

v _(GnB) −v _(MB) ≧V _(tn),  (23)

 MN is in the inversion region. Further, in this case:

(a) when v_(DSn) <v _(Gsn) −V _(tn), MN is in the triode region.

That is, from Eqs. (17) and (18).

when v _(AB) <v _(GnB) −V _(tn),  (24) $\begin{matrix}{i_{Dn} = {K_{n}\left\{ {{2\left( {v_{GSn} - V_{tn}} \right)v_{DSn}} - v_{DSn}^{2}} \right\}}} & (25) \\{\quad {= {K_{n}{\left\{ {{2\left( {v_{GnB} - v_{MB} - V_{tn}} \right)\left( {v_{AB} - v_{MB}} \right)} - \left( {v_{AB} - v_{MB}} \right)^{2}} \right\}.}}}} & (26)\end{matrix}$

(b) when v_(DSn)≧v_(GSn)−V_(tn), MN is in the saturation region. Thatis,

when v _(AB) ≧v _(GnB) −V _(tn),  (27) $\begin{matrix}{i_{Dn} = {K_{n}\left( {v_{GSn} - V_{tn}} \right)}^{2}} & (28) \\{\text{~~~~~} = {{K_{n}\left( {v_{GnB} - v_{MB} - V_{tn}} \right)}^{2}.}} & (29)\end{matrix}$

For MP;

1. MP is in the cutoff region when v_(GSp)>V_(tp). Therefore, from Eq.(19),

when v _(GpB) −v _(MB) >V _(tp),  (30)

 i _(DP)=0.  (31)

2. MP is in the inversion region when v_(GSp)≦V_(tp). Moreover,

(a) If v_(DSp)>v_(GSp)−V_(tp), MP is in the triode region. That is, fromEqs. (19) and (20),

when v _(GpB) <V _(tp),  (32)

i _(Dp) =K _(p){2(v _(MB) −v _(GpB) +V _(tp))v _(MB) −v ² _(MB)}.  (33)

(b) When v_(DSp)≦v_(GSp)−V_(tp), MP is in the saturation region. Thatis,

when v _(GpB) ≧V _(tp),  (34)

i _(Dp) =K _(P)(v _(GpB) −v _(MB) −V _(tp))².  (35)

By use of the above results together with the condition thati_(Λ)=i_(Dn)=i_(Dp), v_(MB) is given as follows. In the following,K_(n)=K_(p)=K is assumed for simplicity.

1. When both MN and MP operate in the triode region, from Eqs. (26) and(33),

v _(MA)={2(V _(tn) −v _(GnB))v _(AB) +v ² _(AB) }/P  (36)

 where

P=2(v _(GpB) −v _(GnB) +V _(tn) −V _(tp))  (37)

 (this is the same in the following description).

2. When MN operates in the triode region and MP operates in thesaturation region, from Eqs. (26) and (35),

v _(MB) ={v ² _(AB)+2(V _(tn) −v _(GnB))v _(AB)+(v _(GpB) −V _(tp))²}/P.  (38)

3. When MN operates in the saturation region and MP operates in thetriode region, from Eqs. (29) and (33),

v _(MB)=−(v _(GnB) −V _(tn))² /P.  (39)

4. When both MN and MP operate in the saturation region, from Eqs. (29)and (35),

v _(MB)={(v _(GpB) −V _(tp) ²−(v _(GnB) −V _(tn))² }/P.  (40)

From the above equations, current i_(Λ) Of FIG. 4 is given as follows,However, in the following, K_(n)=K_(p)=K is assumed for simplicity.

1. When v_(GnB)−v_(MB)<V_(tn) or v_(GpB)−v_(MB)>V_(tp),

i _(Λ)=0.  (42)

2. When v_(GnB)−v_(MB)≧V_(tn) or v_(GpB)−v_(MB)≦V_(tp),

i _(Λ)≠0.  (42)

Moreover,

(a) When v_(AB)<v_(GnB)−V_(tn) and v_(GpB)<V_(tp),

i _(Λ) =K{2(v _(GnB) −v _(MB) −V _(tn))(v _(AB) −v _(MB))−(v _(AB) −v_(MB))²}  (43)

v _(MB)={2(V _(tn) −v _(GnB))v _(AB) +v ² _(AB) }/P.  (44)

(b) When v_(AB)<v_(Gna)−V_(tn) and v_(GpB)≧V_(tp),

i _(Λ) =K{2(v _(GnB) −v _(MB) −V _(tn))(v _(AB) −v _(MB))−(v _(AB) −v_(MB))²}  (45)

v _(MB) ={v ² _(AB)+2(V _(tn) −v _(GnB))v _(AB)+(v _(GpB) −V _(tp))²}/P.  (46)

(c) When v_(AB)≧v_(GnB)−V_(tn) and v_(GpB)<V_(tp),

i _(Λ) =K(v _(GnB) −v _(MA) −V _(tn))²  (47)

v _(MB)=−{(v _(GpB) −V _(tp))² }/P.  (48)

(d) When v_(AB)≧v_(GnB)−V_(tn) and v_(Gpa)≧V_(tp),

i _(Λ) =K(v _(GnB) −v _(MB) −V _(tn))²  (49)

v _(MB)={(v _(GpB) −V _(tp))²−(v _(GnB) −V _(tn))² }/P.  (50)

[2-3] Basic Circuit Configuration for Realizing V-shaped I-VCharacteristics

Next, as shown in FIG. 5, voltages are applied to the terminals of thecore circuit mentioned under section [2-1]. Note that the circuit inFIG. 5 has the same core circuit as in the circuit of FIG. 4, but isplaced upside down. V-shaped I-V characteristics can be realized betweenthe terminals B and A in this circuit. In this case, as shown in FIG. 5,when the respective node points assume the voltages shown in FIG. 5 withrespect to the terminal A, the gate terminal voltages v_(GnA), andv_(GpA) of MN and MP are obtained, by use of Eqs. (2) and (9), from thefollowing equations.

v _(OnA) ={C _(N1A) v _(N1A) +C _(N2)(v _(BA) +v _(N2B))}/(C_(N1)+C_(N2))  (51)

v _(GpA)=(C _(P1) v _(P1A) +C _(P2) v _(P2A))/(C _(P1) +C _(P2))  (52)

In addition, the gate-source voltage v_(GSn) and the drain-sourcevoltage v_(DSn) of MN and the gate-Source voltage v_(GSp) and thedrain-source voltage v_(DSp) of MP are given by the following equations.

v _(GSn) =v _(GnA) −v _(MA)  (54)

v _(DSn) =−v _(MA)  (54)

v _(GSp) =v _(GpA) −v _(MA)  (55)

v _(DSp) =v _(BA) −v _(MA)  (56)

In the same manner as in section [2-2], currents i_(v)=−i_(Dn)=−i_(Dp)in FIG. 5 can be obtained as follows. However, K_(n)=K_(p)=K is assumedfor simplicity.

1. When v_(GnA)−v_(MA)<V_(tn) (MN: cutoff) or v_(GpA)−v_(MA)>V_(tp) (MP:cutoff),

i _(v)=0.  (57)

2. When v_(GnA)−v_(MA)≧V_(tn) and v_(GpA)−v_(MA)≦V_(tp) (MN, MP:inversion),

i _(v)≠0.  (58)

Moreover,

(a) When v_(GnA)>V_(tn) and v_(BA)>v_(GpA)−V_(tp) (MN, MP: triode),

i _(v) =−K{2(v _(MA) −v _(GnA) +V _(tn))v _(MA) −v ² _(MA)}  (59)

v _(MA)={2(v _(GpA) −V _(tp))v _(BA) −v ² _(BA) }/P.  (60)

(b) When v_(GnA)>V_(tn) (MN: triode) and v_(BA)≦v_(GpA)−V_(tp) (MP:saturation),

i _(v) =−K{2(v _(MA) −v _(GnA) +V _(tn))v _(MA) −v ² _(MA)}  (61)

v _(MA)={(v _(GpA) −v _(tp))² }/P.  (62)

(c) When v_(GnA)≦V_(tn) (MN: saturation) and v_(BA)>v_(GpA)−V_(tp) (MP:triode),

i _(v) =−K(v _(GnA) −v _(MA) −V _(tn))²  (63)

v _(MA)={2(v _(OpA) −V _(tp))v _(BA) −v ² _(BA)−(v _(GnA) −V _(tn))²}/P.  (64)

(d) When v_(GnA)≦V_(tn) and v_(BA)≦v_(GpA)−V_(tp) (MN, MP: saturation),

i _(v) =−K(v _(GnA) −v _(MA) −V _(tn))²  (65)

v _(MA)={(v _(GpA) −V _(tp))² −(v _(GnA) −V _(tn))² }/P.  (66)

[2-4] Improvement on Λ-Type I-V Nonlinear Resistor Circuit

Next will be described an improvement which is performed on the Λ-typeI-V nonlinear resistor basic circuit described in section [2-2] andwhich Provides broader I-V characteristics.

Voltage sources v_(X) and v_(Y) are added to the terminals A and B inthe circuit of FIG. 4, respectively. Sixteen different combinations arepossible for connecting the voltages sources, as shown in FIGS.6(a)-6(p). The shaded box in each of FIGS. 6(a)-6(p) represents the corecircuit shown in FIG. 3. Since the circuits of FIGS. 6(a)-6(p) havesimilar characteristics, only the circuit of FIG. 6(f) will be describedin detail as an example. The circuit is shown in FIG. 7.

Voltages of respective nodes with respect to the terminal Y as depictedin FIG. 7 are given by

v _(GnY)=(C _(N1) v _(N1Y) +C _(N2) v _(N2Y))/(C _(N1) +C _(N2))  (67)

 v _(GpY) ={C _(P1)(v _(XY) −v _(X) +v _(P1A))+C _(P2) v _(P2Y)}/(C_(P1) +C _(P2))  (68)

v _(DSn) =v _(XY) −v _(X) −v _(MY)  (69)

v _(DSp) =v _(Y) −v _(MY)  (70)

v _(GSn) =v _(GnY) −v _(MY)  (71)

v _(GSp) =v _(GpY) −v _(MY)  (72)

Moreover, the following voltage relationships are found between FIG. 4and FIG. 7.

v _(AB) =v _(XY) −v _(X) −v _(Y)  (73)

v _(MB) =v _(MY) −v _(Y)  (74)

v _(N1B) =v _(N1Y) −v _(Y)  (75)

v _(N2B) =v _(N2Y) −v _(Y)  (76)

v _(P2B) =v _(P2Y) −v _(Y)  (77)

v _(GnB) =v _(GnY) −v _(Y)  (78)

v _(GpB) =v _(GpY) −v _(Y)  (79)

By substitution of the above equations into corresponding equations insection [2-2], equations for operations of circuit of FIG. 7 areobtained as follows. Again, K_(n)=K_(p)=K is assumed for simplicity inthe following.

1. When v_(GnY)−v_(MY)<V_(tn) (MN: cutoff) or v_(GpY)−v_(MY)>V_(tp) (MP:cutoff),

i _(Λ)=0  (80)

2. When v_(GnY)−v_(MY)≧V_(tp) and v_(GpY)−v_(MY)≦V_(tp) (MN, MP:inversion),

i _(Λ)≠0.  (81)

Moreover,

(a) When v_(XY)<v_(X)+v_(GnY)−V_(tn) and v_(GpY)<v_(Y)+V_(tp) (MN, MP:triode),

i _(Λ) =K{2(v _(GnY) −v _(MY) −V _(tn))(v _(XY) −v _(X) −v _(MY))−(v_(XY) −v _(X) −v _(MY))²}  (82)

v _(MY) =[v ² _(XY)+2(V _(tn) +v _(GnY))v _(XY)+{2(v _(GnY) −v _(XY) −V_(tn))+v _(X) }v _(X)+{2(v _(GpY) −V _(tp))−v _(Y) }v _(Y) ]/Q  (83)

 where

Q=2(v _(GpY) −v _(GnY) +V _(tn) −V _(tp)).  (84)

 (This is the same in the following description.)

(b) When v_(XY)<v_(X)+v_(GnY)−V_(tn) (MN: triode) andv_(GpY)≧v_(Y)+V_(tp) (MP: saturation),

i _(Λ) =K{2(v _(GnY) −v _(MY) −V _(tn))(v _(XY) −v _(X) −v _(MY))−(v_(XY) −v _(X) −v _(MY))²}  (85)

v _(MY) =[v ² _(XY)+2(V _(tn) +v _(GnY))v _(XY)+{2(v _(GnY) −v _(XY) −V_(tn))+v _(X) }v _(X)+(v _(GpY) −V _(tp))² /Q.  (86)

(c) When v_(XY)≧v_(X)+v_(GnY)−V_(tn) (MN: saturation) andv_(GpY)≧v_(Y)+V_(tp) (MP: triode),

i _(Λ) =K(v _(GnY) −v _(MY) −V _(tn))²  (87)

v _(MY)=[{2(v _(GpY) −V _(tp))−v _(Y) }v _(Y)−(v _(GnY) −V _(tn))²]/Q  (88)

(d) When v_(XY)≧v_(x)+v_(GnY)−V_(tn) and v_(GpY)≧v_(Y)+V_(tp) (MN, MP:saturation),

i _(Λ) =K(v _(GnY) −v _(MY) −V _(tn))²  (89)

v _(MA)={(v _(GpY) −V _(tp))²−(v _(GnY) −V _(tn))² }/Q  (90)

[2-5] Improvement on V-type I-V Nonlinear Resistor Circuit

In a similar manner as in the previous section, the V-type I-V nonlinearresistor basic circuit described in section [2-3] was improved.

Voltage sources v_(X) and v_(Y) are added to the terminals A and B inthe circuit of FIG. 5, respectively. Sixteen different combinations arepossible for connecting the voltages sources, as shown in FIGS.8(a)-8(p). The shaded box in each of FIGS. 8(a)-8(p) represents the corecircuit shown FIG. 3. Note that the core circuit is shown upside down.Since the circuits of FIGS. 8(a)-8(p) have similar characteristics, onlythe circuit of FIG. 8(f) will be described in detail as an example. Thecircuit is shown in FIG. 9.

Voltages of respective nodes with respect to the terminal Y as depictedin FIG. 9 are given by

v _(GnY) ={C _(N1) v _(N1Y) +C _(N2)(v _(XY) −v _(X) +v _(N2B))}/(C_(N1) +C _(N2))  (91)

v _(GpY) ={C _(P1) v _(P1Y) +C _(P2Y) v _(P2Y)}/(C _(P1) +C _(P2))  (92)

v _(DSn) =v _(Y) −v _(MY)  (93)

v _(DSp) =v _(XY) −v _(X) −v _(MY)  (94)

v _(GSn) =v _(GnY) −v _(MY)  (95)

v _(GSp) =v _(GpY) −v _(MY)  (96)

Moreover, the following voltage relationships are found between FIG. 5and FIG. 9.

v _(BA) =v _(XY) −v _(X) −v _(Y)  (97)

v _(MA) =v _(MY) −v _(Y)  (98)

v _(N1A) =v _(N1Y) −v _(Y)  (99)

v _(P1A) =v _(P1Y) −v _(Y)  (100)

v _(P2A) =v _(P2Y) −v _(Y)  (101)

v _(GnA) =v _(GnY) −v _(Y)  (102)

v _(GpA) =v _(GpY) −v _(Y)  (103)

By substitution of the above equations into corresponding equations insection [2-3], operation equations of the circuit of FIG. 9 are obtainedas follows. In the following, K_(n)=K_(p)=K is assumed for simplicity.

1. When v_(GnY)−v_(MY)<V_(tn) (MN: cutoff) or v_(GpY)−v_(MY)>V_(tp) (MP:cutoff),

i _(v)=0  (104)

2. When v_(GnY)−v_(MY)≧V_(tn) and v_(CpY)−v_(MY)≦V_(tp) (MN, MP:inversion),

i _(v)≠0.  (105)

Moreover,

(a) When v_(Y)<v_(GnY)−V_(tn) and v_(XY)>v_(X)+v_(GpY)−V_(tp) (MN, MP:triode),

i _(v) =K{2(v _(GnY) −v _(MY) −V _(tn))(v _(Y) −v _(MY))−(v _(Y) −v_(MY))²}  (106)

v _(MY) −[−v ² _(XY)+2(v _(GpY) −V _(tp))v _(XY)+{2(v _(XY) −v _(GpY) +V_(tp))−v _(X) }v _(X)+{2(V _(tn) −v _(GnY))+v _(Y) }v _(Y) ]/Q  (107)

(b) When v_(Y)<v_(GnY)−V_(tn) (MN: triode) andv_(XY)≦v_(X)+v_(GpY)−V_(tp) (MP: saturation),

i _(v) =K{2(v _(GnY) −v _(MY) −V _(tn))(v _(Y) −v _(MY))−(v _(Y) v_(MY))²}  (108)

v _(MY)=[2(V _(tn) −v _(GnY))+v _(Y))v _(Y)+(v _(GpY) −V _(tp))²]/Q  (109)

(c) When v_(Y)≧v_(GnY)−V_(tn) (MN: saturation) andv_(XY)>v_(X)+v_(GpY)−V_(tp) (MP: triode),

i _(v) =K(v _(GnY) −v _(MY) −V _(tn))²  (110)

v _(MY) =[−v ² _(XY)+2(v _(GpY) −V _(tp))v _(XY)+{2(v _(XY) −v _(GpY) +V_(tp))−v _(X) }v _(X)−(v _(GnY) −V _(tn))² ]/Q  (111)

(d) When v_(Y)≧v_(GnY)−V_(tn) and v_(XY)≦v_(X)+v_(GpY)−V_(tp) (MN, MP:saturation),

i _(v) =K(v _(GnY) −v _(MY) −V _(tn))²  (112)

v _(MY)={(v _(GpY) −V _(tp))²−(v _(GnY) −V _(tn))² }/Q  (113)

[3] Numerical Simulations

I-V characteristics of circuits of FIG. 7 were calculated throughcomputer simulations utilizing the equations obtained in section [2].Device parameters used in the simulations are given below,

K _(n) =K _(p)=300 μA/V ²

V _(tn)=0.7 V

v _(tp)=−0.7 V

 C _(N1) =C _(N2) =C _(P1) C _(P2)=0.1 μF

FIG. 10 shows i_(Λ)-v_(XY) characteristics, where v_(N1Y) and v_(X) areparameters, v_(P2Y)=−4 V, v_(N2Y)=2.5 V, and v_(P1A)=v_(Y)=0 V.

Further, FIG. 11 shows i_(Λ)-v_(XY) characteristics, where v_(Y) is aparameter, v_(P2Y)=−4 V, v_(N1Y)=3 V, v_(P1A)=v_(X)=0 V, andv_(N2Y)=v_(Y).

Next, results of a simulation performed for the circuit of FIG. 9 willbe described.

FIG. 11 shows i_(Λ)-v_(XY) characteristics of the circuit of FIG. 7,where v_(Y) is a parameter.

FIG. 12 shows i_(v)-v_(XY) characteristics, where v_(N1Y) and v_(X) areparameters, v_(P2Y)=−4 V, and v_(P1Y)=v_(N2B)=v_(Y)=0 V.

Moreover, FIG. 13 shows i_(v)-v_(XY) characteristics, where v_(Y) is aparameter, v_(P2Y)=−4 V, v_(N1Y)=2.5 V, v_(N2B)=v_(X)=0V, andv_(N2Y)=v_(Y).

The numerical simulations have confirmed that the circuits of thepresent invention show Λ- and V-shaped I-V characteristics. It has alsobeen proved that the I-V characteristics can be controlled by externalvoltages and that various nonlinear resistor characteristics can beobtained as shown in FIG. 14.

[4] Experiments Performed by Use of Discrete Elements

Prototypes of the circuits of the present invention were fabricated byuse of discrete electronic components. As MOSFETs MN and MP in thecircuits, FETs in CMOS-IC HD14007UBP were used. In addition, couplingcapacitances are assumed as C_(N1)=C_(N2)=C_(P1)=C_(P2)=0.1 μF.

FIG. 15 shows measured results of i_(Λ)-v_(XY) characteristics of thecircuit of FIG. 7, where v_(N1Y) and v_(X) are parameters, v_(P2Y)=−4 V,v_(N2Y)=3.2 V, and v_(P1A)=v_(Y)=0 V. The results correspond to those ofnumerical simulations shown in FIG. 10.

Further, FIG. 16 shows i_(Λ)-v_(XY) characteristics of the circuit ofFIG. 7, where v_(Y) is a parameter, v_(N1Y)=3.5 V, v_(P2A)=−4 V,v_(P1A)=v_(X)=0 V, and v_(N2Y)=v_(Y). The results correspond to those ofnumerical simulations shown in FIG. 11.

Then, FIG. 17 shows i_(v)-v_(XY) characteristics of the circuit of FIG.9, where v_(N1Y) and v_(X) are parameters, v_(P2Y)=−4V, andv_(N2B)=v_(P1Y)=v_(Y)=0 V. The results correspond to those of numericalsimulations shown in FIG. 12.

Moreover, FIG. 18 shows i_(v)-v_(XY) characteristics of the circuit ofFIG. 9, where v_(Y) is a parameter, v_(P2Y)=−4 V, v_(N1Y)=3.2 V,v_(N2B)=v_(X)0 V, and v_(N2Y)=v_(Y). The results correspond to those ofnumerical simulations shown in FIG. 13.

The above experimental results are qualitatively consistent with theresults of the numerical simulations described in the previous section.That is, the experiments have also proved that the circuits of thepresent invention show nonlinear resistor characteristics.

As has been described, a nonlinear resistor circuit which can beintegrated by use of a standard CMOS process was obtained. According tothe circuit of the present invention, a variety of Λ- or V-shaped I-Vcharacteristics can be provided through control of external voltages.

Therefore, the circuit of the present invention may be applicable tovarious signal processing circuits, oscillators, impedance simulationcircuits, memory circuits, logic circuits, and chaos generatingcircuits. Moreover, the circuit of the present invention is consideredapplicable to integration of pulse-type hardware chaos neuron circuits(See Fifth reference),

Furthermore, the above application circuits can be made compact throughintegration by use of a floating-gate technique (see sixth reference andseventh reference).

The present invention is not limited to the above-described embodiments.Numerous modifications and variations of the present invention arepossible in light of the spirit of the present invention, and they arenot excluded from the scope of the present invention.

As has been described, the present invention provides the followingeffects.

(1) Λ-type and V-type nonlinear resistance characteristics are bothobtained by use of the same circuit configuration.

(2) The nonlinear resistance characteristics can be varied throughapplication of an external control voltage.

(3) Since only enhancement-type MOSFETs are used, the nonlinear resistorcircuit can be fabricated in the form of an integrated circuit in astandard CMOS process.

(4) Since nonlinear capacitors can be used for input couplingcapacitors, the nonlinear resistor circuit can be fabricated in the formof an integrated circuit in an inexpensive CMOS process in which linearcapacitors are not available.

(5) When the size of MOSFETs used in the nonlinear resistor circuit isreduced, the input coupling capacitance can be reduced accordingly. Theparasitic capacitance C₀ (see section [1-1]) does not affect theessential characteristics of the circuit. Accordingly, the circuit canbe made compact with ease.

(6) Use of vMOSFETs enables the circuit to be rendered very compact,thereby enabling efficient integration of the circuit.

Industrial Applicability

The nonlinear resistor circuit using capacitively-coupled multi-inputmosfets according to the present invention is applicable to varioustypes of signal processing circuits, oscillators, inductance simulationcircuits, memory circuits, logic circuits, and chaos generators.

What is claimed is:
 1. A nonlinear resistor circuit using capacitivelycoupled multi-input MOSFETs, comprising a core circuit which has anonlinear resistance characteristic and which comprises: (a) anenhancement-type N-channel MOSFET having a capacitively-coupledmulti-input gate terminal, (b) an enhancement-type P-channel MOSFEThaving a capacitively-coupled multi-input gate terminal, and (c) thesource terminals of the MOSFETs being connected with each other,wherein, a fifth potential is provided between the drain terminal of theN-channel MOSFET and a first input/output terminal; a sixth potential isprovided between the drain terminal of the P-channel MOSFET and a secondinput/output terminal; a first potential is provided between the drainterminal of the N-channel MOSFET and a first capacitor connected to thegate of the P-channel MOSFET or between the first input/output terminaland the first capacitor; a second potential is provided between thedrain terminal of the P-channel MOSFET and a second capacitor connectedto the gate of the P-channel MOSFET or between the second input/outputterminal and the second capacitor; a third potential is provided betweenthe drain terminal of the P-channel MOSFET and a third capacitorconnected to the gate of the N-channel MOSFET or between the secondinput/output terminal and the third capacitor; and a fourth potential isprovided between the drain terminal of the P-channel MOSFET and a fourthcapacitor connected to the gate of the N-channel MOSFET or between thesecond input/output terminal and the fourth capacitor, so that a Λ-typecurrent voltage characteristic, which is varied through application ofan external control voltage, is obtained.
 2. A nonlinear resistorcircuit using capacitively-coupled multi-input MOSFETs, comprising acore circuit which has a nonlinear resistance characteristic and whichcomprises: (a) an enhancement-type P-channel MOSFET having acapacitively-coupled multi-input gate terminal, (b) an enhancement-typeN-channel MOSFET having a capacitively-coupled multi-input gateterminal, and (c) the source terminals of the MOSFETs being connectedwith each other, wherein, a fifth potential is provided between thedrain terminal of the P-channel MOSFET and a first input/outputterminal; a sixth potential is provided between the drain terminal ofthe N-channel MOSFET and a second input/output terminal; a firstpotential is provided between the drain terminal of the P-channel MOSFETand a first capacitor connected to the gate of the N-channel MOSFET orbetween the first input/output terminal and the first capacitor; asecond potential is provided between the drain terminal of the N-channelMOSFET and a second capacitor connected to the gate of the N-channelMOSFET or between the second input/output terminal and the secondcapacitor; a third potential is provided between the drain terminal ofthe N-channel MOSFET and a third capacitor connected to the gate of theP-channel MOSFET or between the second input/output terminal and thethird capacitor; and a fourth potential is provided between the drainterminal of the N-channel MOSFET and a fourth capacitor connected to thegate of the P-channel MOSFET or between the second input/output terminaland the fourth capacitor so that a V-type current voltagecharacteristic, which is varied through application of an externalcontrol voltage, is obtained.